Difference between revisions of "Electron Detector DAQ"
| Line 1: | Line 1: | ||
| + | == Introduction == | ||
| + | |||
#[[Nomenclature Conventions]] | #[[Nomenclature Conventions]] | ||
#Pin Plan of v1495 | #Pin Plan of v1495 | ||
| Line 11: | Line 13: | ||
## [[pin mappings in Mezzanine A395D]] | ## [[pin mappings in Mezzanine A395D]] | ||
| − | == Firmware Revision History == | + | |
| + | == Trigger Formation == | ||
| + | The signals received from 96 strips of each detector plane are processed to form a single trigger in each trigger window. Signals from strips 1-4 are OR-ed to form the first sub-cluster, strips 5-8 are OR-ed again to form the 2nd sub-cluster and so on. The first and second sub-clusters are OR-ed to form the signal called plane-1's cluster-1 output. The second and third sub-clusters are OR-ed again to form the signal called plane-1's cluster-2 output. Following this pattern, there is a total of 7 signal clusters formed from each plane. The output from corresponding signal clusters of all 4 planes are checked for the trigger condition in the coincidence time window set by the pulse-width of Delay-line(parameter ''pwdl''). | ||
| + | |||
| + | For instance, if the parameters | ||
| + | event-trigger = 2 | ||
| + | accum-trigger = 3 | ||
| + | PWDL = 100 ns | ||
| + | then the master board will generate the event trigger output only if at least 2 of the 4 clusters(one coming from each plane) are found high during the rising edge of the inbuilt 25ns clock. The occurrence of above condition will be checked 4 times at intervals of 25 ns because the coincidence time(PWDL) is set to 100 ns (4x25) | ||
| + | |||
| + | [[Image:Edet trig formation.png]] | ||
| + | |||
| + | == v1495 Firmware Revision History == | ||
=== Slave Board === | === Slave Board === | ||
Revision as of 23:00, 22 October 2010
Introduction
- Nomenclature Conventions
- Pin Plan of v1495
- Library of functions
- Signal Flow Layout
- Output data structure in CODA
- Generic info: v1495
Trigger Formation
The signals received from 96 strips of each detector plane are processed to form a single trigger in each trigger window. Signals from strips 1-4 are OR-ed to form the first sub-cluster, strips 5-8 are OR-ed again to form the 2nd sub-cluster and so on. The first and second sub-clusters are OR-ed to form the signal called plane-1's cluster-1 output. The second and third sub-clusters are OR-ed again to form the signal called plane-1's cluster-2 output. Following this pattern, there is a total of 7 signal clusters formed from each plane. The output from corresponding signal clusters of all 4 planes are checked for the trigger condition in the coincidence time window set by the pulse-width of Delay-line(parameter pwdl).
For instance, if the parameters
event-trigger = 2 accum-trigger = 3 PWDL = 100 ns
then the master board will generate the event trigger output only if at least 2 of the 4 clusters(one coming from each plane) are found high during the rising edge of the inbuilt 25ns clock. The occurrence of above condition will be checked 4 times at intervals of 25 ns because the coincidence time(PWDL) is set to 100 ns (4x25)
v1495 Firmware Revision History
Slave Board
All the documented firmware revisions that are updated here, can be found in the SVN mentioning their revision numbers.
- 2005: fully working and checked with Readout.
- 2006[Jan 29 '10]: added an added feature of minimum width rejection in the Reconditioning module of the firmware
- After moving to the 32 bit version for slave boards, the firmware # starts from 3201 onwards. As of Oct 20, we are using Revision number 3210 on the slave boards. Notice that Revision version 320F (the just previous version) had a bug.
Master Board
- AA07 : unlike v.AA06, the buf_busy signal does not affect the generation of trigger signals from the master board.(needs to be investigated further)
