Difference between revisions of "Slave v1495"

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== A port ==
 
== A port ==
  
 +
The A port is an '''input''' and receives LVDS from QWAD boards in the tunnel via the 200' cable.
 +
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
! pin #: DD strip #
 
! pin #: DD strip #
Line 62: Line 64:
 
|}
 
|}
  
−
The B, D and E follow the exact same pattern as A port.  
+
The B, D and E ports follow the exact same pattern as A port.  
  
 
----
 
----
  
 
== C-port ==
 
== C-port ==
−
The C-port output on slave-1 has the following signals.
+
The C-port is used as an '''output''' on slave-1 and has the following signals.
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
! pin #
 
! pin #
 
! corresponding signal
 
! corresponding signal
 
|-
 
|-
−
| C(32): pl_delay signal in strip 32
+
| C(32): st21,p4 & st19,p3
−
| C(31): pl_delay signal in strip 31
+
| C(31): st20,p4 & st18,p3
 
|-
 
|-
−
| C(30): pl_delay signal in strip 30
+
| C(30): st19,p4 & st17,p3
−
| C(29): pl_delay signal in strip 29
+
| C(29): st18,p4 & st16,p3
 
|-
 
|-
−
| C(28): pl_delay signal in strip 28
+
| C(28): st17,p4 & st15,p3
−
| C(27): pl_delay signal in strip 27
+
| C(27): st16,p4 & st14,p3
 
|-
 
|-
−
| C(26): pl_delay signal in strip 26
+
| C(26): st15,p4 & st13,p3
−
| C(25): pl_delay signal in strip 25
+
| C(25): st14,p4 & st12,p3
 
|-
 
|-
−
| C(24): pl_delay signal in strip 24
+
| C(24): st13,p4 & st11,p3
−
| C(23): pl_delay signal in strip 23
+
| C(23): st12,p4 & st10,p3
 
|-
 
|-
−
| C(22): pl_delay signal in strip 22
+
| C(22): st11,p4 & st9,p3
−
| C(21): pl_delay signal in strip 21
+
| C(21): st10,p4 & st8,p3
 
|-
 
|-
−
| C(20): pl_delay signal in strip 20
+
| C(20): st9,p4 & st7,p3
−
| C(19): pl_delay signal in strip 19
+
| C(19): st8,p4 & st6,p3
 
|-
 
|-
−
| C(18): pl_delay signal in strip 18
+
| C(18): st7,p4 & st5,p3
−
| C(17): pl_delay signal in strip 17
+
| C(17): st6,p4 & st4,p3
 
|-
 
|-
−
| C(16): buffer is Full
+
| C(16): Pattern buffer busy
−
| C(15): pipeline delay of strip-5
+
| C(15): pipeline delay of strip-5,plane 2
 
|-
 
|-
−
| C(14): pipeline delay of strip-4
+
| C(14): pipeline delay of strip-4,plane 2
−
| C(13): pipeline delay of strip-3
+
| C(13): pipeline delay of strip-3,plane 2
 
|-
 
|-
−
| C(12): pipeline delay of strip-2
+
| C(12): pipeline delay of strip-2,plane 2
−
| C(11): pipeline delay of strip-1
+
| C(11): pipeline delay of strip-1,plane 2
 
|-
 
|-
 
| C(10): independent event pre-trigger in this slave
 
| C(10): independent event pre-trigger in this slave
−
| C(9): OR of bottom 4 strips(# 28-32) in this part of plane-4
+
| C(9): OR of bottom 2 strips(# 28-32) in this part of plane-4
 
|-
 
|-
−
| C(8): OR of bottom 4 strips(# 28-32) in this part of plane-3
+
| C(8): OR of bottom 2 strips(# 28-32) in this part of plane-3
−
| C(7): OR of bottom 4 strips(# 28-32) in this part of plane-2
+
| C(7): OR of bottom 2 strips(# 28-32) in this part of plane-2
 
|-
 
|-
−
| C(6): OR of bottom 4 strips(# 28-32) in this part of plane-1
+
| C(6): OR of bottom 2 strips(# 28-32) in this part of plane-1
−
| C(5): OR of top 4 strips(# 1-4) in this part of plane-4
+
| C(5): OR of top 2 strips(# 1-4) in this part of plane-4
 
|-
 
|-
−
| C(4): OR of top 4 strips(# 1-4) in this part of plane-3
+
| C(4): OR of top 2 strips(# 1-4) in this part of plane-3
−
| C(3): OR of top 4 strips(# 1-4) in this part of plane-2
+
| C(3): OR of top 2 strips(# 1-4) in this part of plane-2
 
|-
 
|-
−
| C(2): OR of top 4 strips(# 1-4) in this part of plane-1
+
| C(2): OR of top 2 strips(# 1-2) in this part of plane-1
 
| C(1): accumulation pre-trigger in this slave
 
| C(1): accumulation pre-trigger in this slave
 
|}
 
|}
Line 124: Line 126:
  
 
== F-port ==
 
== F-port ==
−
The F-port is set to receives NIM based input signals(originated from TS)
+
The F-port is set to receives NIM based '''input''' signals(originated from TS)
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
! pin #
 
! pin #
 
! corresponding signal
 
! corresponding signal
 
|-
 
|-
−
| F(8)-F(4)
+
| F(8)
 +
| sync signal(to be used for diagnosis)
 +
|-
 +
| F(7)-F(4)
 
| unused
 
| unused
 
|-
 
|-
 
| F(3)
 
| F(3)
−
| Event mode trigger
+
| event-trig input
 
|-
 
|-
 
| F(2)
 
| F(2)
−
| Accumulation mode trigger
+
| accum-trig input
 
|-
 
|-
 
| F(1)
 
| F(1)
Line 145: Line 150:
  
 
== G-port ==
 
== G-port ==
−
The G-port set for receiving NIM input signals (originated from Master v1495)
+
The G-port set for receiving NIM based '''input''' signals  
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
{| style="color:maroon; background-color:#ffffff;" cellpadding="10" cellspacing="0" border="1"
 
! pin #
 
! pin #
Line 151: Line 156:
 
|-
 
|-
 
|G(2)
 
|G(2)
−
|MPS
+
|MPS L1A (the Level-1-Accept for MPS generated by TS)
 
|-
 
|-
 
|G(1)
 
|G(1)
−
|Global Clock
+
|Global Clock (originated from Master v1495)
 
|}
 
|}
  
 
All other slaves also follow the same pattern for all their input/output ports.
 
All other slaves also follow the same pattern for all their input/output ports.

Latest revision as of 12:50, 30 April 2011

Slave-1:

The A, B, D and E ports take LVDS, 32 bit input signal information from the top 32 strips of planes 1, 2, 3 and 4 respectively. 

 Strips on detector and Pins on the input port are counted from 1 onwards (instead of 0).

Pin 1 is indicated by a white arrow on the port of v1495. The pattern in which signals are given into the pins are as follows:


A port

The A port is an input and receives LVDS from QWAD boards in the tunnel via the 200' cable.

pin #: DD strip # pin #: DD strip #
A(32): strip 32 A(16): strip 31
A(31): strip 30 A(15): strip 29
A(30): strip 28 A(14): strip 27
A(29): strip 26 A(13): strip 25
A(28): strip 24 A(12): strip 23
A(27): strip 22 A(11): strip 21
A(26): strip 20 A(10): strip 19
A(25): strip 18 A(9): strip 17
A(24): strip 16 A(8): strip 15
A(23): strip 14 A(7): strip 13
A(22): strip 12 A(6): strip 11
A(21): strip 10 A(5): strip 9
A(20): strip 8 A(4): strip 7
A(19): strip 6 A(3): strip 5
A(18): strip 4 A(2): strip 3
A(17): strip 2 A(1): strip 1

The B, D and E ports follow the exact same pattern as A port.

C-port

The C-port is used as an output on slave-1 and has the following signals.

pin # corresponding signal
C(32): st21,p4 & st19,p3 C(31): st20,p4 & st18,p3
C(30): st19,p4 & st17,p3 C(29): st18,p4 & st16,p3
C(28): st17,p4 & st15,p3 C(27): st16,p4 & st14,p3
C(26): st15,p4 & st13,p3 C(25): st14,p4 & st12,p3
C(24): st13,p4 & st11,p3 C(23): st12,p4 & st10,p3
C(22): st11,p4 & st9,p3 C(21): st10,p4 & st8,p3
C(20): st9,p4 & st7,p3 C(19): st8,p4 & st6,p3
C(18): st7,p4 & st5,p3 C(17): st6,p4 & st4,p3
C(16): Pattern buffer busy C(15): pipeline delay of strip-5,plane 2
C(14): pipeline delay of strip-4,plane 2 C(13): pipeline delay of strip-3,plane 2
C(12): pipeline delay of strip-2,plane 2 C(11): pipeline delay of strip-1,plane 2
C(10): independent event pre-trigger in this slave C(9): OR of bottom 2 strips(# 28-32) in this part of plane-4
C(8): OR of bottom 2 strips(# 28-32) in this part of plane-3 C(7): OR of bottom 2 strips(# 28-32) in this part of plane-2
C(6): OR of bottom 2 strips(# 28-32) in this part of plane-1 C(5): OR of top 2 strips(# 1-4) in this part of plane-4
C(4): OR of top 2 strips(# 1-4) in this part of plane-3 C(3): OR of top 2 strips(# 1-4) in this part of plane-2
C(2): OR of top 2 strips(# 1-2) in this part of plane-1 C(1): accumulation pre-trigger in this slave

F-port

The F-port is set to receives NIM based input signals(originated from TS)

pin # corresponding signal
F(8) sync signal(to be used for diagnosis)
F(7)-F(4) unused
F(3) event-trig input
F(2) accum-trig input
F(1) Helicity (H+)

G-port

The G-port set for receiving NIM based input signals

pin # corresponding signal
G(2) MPS L1A (the Level-1-Accept for MPS generated by TS)
G(1) Global Clock (originated from Master v1495)

All other slaves also follow the same pattern for all their input/output ports.

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