Photon Detector
Data acquisition
The photon detector data acquisition is based around the SIS3320 250 MHz sampling ADC with built-in accumulator registers. This allows us to integrate the full signal over the full helicity window, while having access to individual pulses in the form of their 250 MHz (4 ns) samples.
A few other modules provide redundant and backup data acquisition. We have a Caen V792 QDC module that buffers the integrated and gated photon detector pulses in each helicity window. A Caen V775 TDC is intended for the coincidence analysis between photon and electron detector.
One scaler keeps track of how many photon detector events occurred in each helicity window, and a second scaler count the number of sampling ADC samples between each photon detector event and the start of the integration window.
The read-out is done at the end of each helicity window, triggered by the MPS signal from MCC (or potentially the HAPPEX timing board).
- The primary information, the integrated signal from the sampling ADC is read out first. The memory mapping of the current event is stored for future read-out. The double buffer of the ADC is swapped to allow for taking a new event without overwriting the current event information, and the sampling ADC external trigger is armed again in anticipation of the next helicity window.
- Then the helicity window scaler is read out. Only the first four words need to be read out because the other channels are not connected.
- Next the photon detector event scaler is read out. There is one set of buffered counts for every photon event, so the information from the previous step is used. Only the first four words need to be read out because the other channels are not connected. DMA access can speed up this copy operation.
- If required, the buffered V792 and V775 events are read out. Threshold suppression of these modules can be used to speed up this operation.
- Finally the events in the sampling ADC buffer are read out. DMA access can speed up this copy operation.
The SIS3320 sampling ADC is armed for sampling as soon as the accumulators are read out and the buffer has been swapped. This is early enough to be ready by the time the integration window starts.
The photon detector events are suppressed until after the scalers, V792 and V775 are read out. This ensures that we do not buffer more events than we can handle in the read-out cycle before the next helicity trigger arrives.
Trigger supervisor crate
The trigger supervisor crate is responsible for the helicity and quartet streams. Two methods for helicity read-out are used: user bit mode (SIS3801) and input register mode (SIS3600). The user bits are sometimes latched at the wrong time (one helicity window off), so the input register bit should be trusted. The input register is latched with the rising edge of the ~MPS signal. An additional scaler (STR7200) is used to count the helicity pattern phase. These scaler channels are cleared by the combination of QRT && ~MPS.
In the trigger supervisor crate there are two scaler modules (SIS3801) that read the V/F signals with the BCM and BPM information.
CsI Crystal
After polishing, the transparency improved: 
Detector assembly and test
The CsI crystal was wrapped with aluminized mylar and tedlar. The PMT was then glued.
The test results are [here]
