Photon Detector

Introduction

The photon detector is a block of pure caesium-iodide (CsI). Compton photons (and other high-energetic particles) cause scintillation in the CsI. The scintillation light output of pure CsI is lower than its tellurium-doped cousins (CsI:Tl), but it is much faster with a characteristic time of 16 ns. This allows higher rate operation without having to worry too much about pile-up or event stacking. The scintillation light is detected by a 3 inch photomultiplier tube (PMT) at the end of the CsI block. The signal travels through a low-loss coaxial cable to the counting house where it is digitized.

Undoped CsI Crystal

The crystal is a cuboid of 4 inch by 4 inch by 12 inch, with a 1.5 inch deep cylindrical transition to the 3 inch wide PMT. All side surfaces are polished to increase total internal reflection, except for the window on which the PMT is glued. To increase the scattering of light from inside the crystal to the PMT, that particular surface is roughened.

Two similar crystals/PMT assemblies are available.

Photomultiplier tube

The photomultiplier tube (PMT) is a Hamamatsu R4885 3 inch assembly with a gain of 5e6. The operating high voltage of the tube is between 1700 V and 2300 V (maximum is 2500 V).

For the initial tests at HIgS the Photonis XP3462 photomultiplier with corresponding resistive base XP3462B was used.

Setting the high-voltage

The high voltage for photon detector is set in the Moller high voltage GUI. This GUI is at cvxwrks@cdaql4:$EPSHV/tk/hv.tcl. The photon detector is on channel 6 in the group Compton, and is labeled "Compton6". The current is indicated in nA, and currents of 400 uA at 1700 V without beam are reasonable.

Data acquisition

Temporary Moller data acquisition

For commissioning the signals from the Compton photon detector are plugged into the Moller data acquisition. The most useful features are the scaler server and associated rate monitoring tool and the ability to take ADC spectra.

• To start the rate monitoring, run the program cdaq@cdaql3:~/moller/compton_mon. The photon detector shows up in the 'Coincidences' row. The current measured by BCM3 is unreliable. If no rates are shown, the ROC vmec8 might need to be rebooted. You will have to reboot it by using rebootpanel, not by typing reboot at the vmec8 VxWorks prompt.
• To start the CODA DAQ, run codamaster on cdaq@cdaql3. Start the components and start a run. Analyze the run with ~/moller/anal/qweak/fortran/replay_moller runnumber, and look at the plots in paw++ with exe mscan runnumber. The relevant histograms are 19 and 20 (ADC for negative and positive helicity). The ADC is a 10 channel ADC so there are 1024 channels. A 'reasonable' pulse of 150 mV corresponds to approximately 250 channels.

Compton data acquisition

The photon detector data acquisition is based around the SIS3320 250 MHz sampling ADC with six built-in accumulator registers (firmware version 103A). This allows us to integrate the full signal output over the helicity window even with overlapping pulses, while having access to individual pulses through their 250 MHz (4 ns) samples.

A few other modules provide redundant and backup data acquisition. We have a Caen V792 QDC module that buffers the integrated gated photon detector pulses in each helicity window. A Caen V775 TDC is intended for the coincidence analysis between photon and electron detector. One scaler keeps track of how many photon detector events occurred in each helicity window, and a second scaler count the number of sampling ADC samples between each photon detector event and the start of the integration window.

The sampling ADC clock of 250 MHz is down-sampled to allow it to be counted in the scaler. Currently this downsampling limits the clock rate of the sampling ADC to 100 MHz. The sampling ADC also has an issue to be set to 250 MHz.

The sampling ADC is set up to collect one long event from LEMO start to LEMO stop in a circular buffer of 16M samples long. In a 1 ms helicity window the buffer does not wrap around, and error are detected by the sampling ADC zero accumulator sample sum.

The read-out is done at the end of each helicity window, triggered by the MPS signal from MCC (or potentially the HAPPEX timing board).

1. The primary information, the integrated signal from the sampling ADC, is read out first. The memory mapping of the current event is stored for future read-out. The double buffer of the ADC is swapped to allow for taking a new event without overwriting the current event information, and the sampling ADC external trigger is armed again in anticipation of the next helicity window.
2. Then the helicity window scaler is read out. Only the first 'few' words need to be read out because the other channels are not connected.
3. Next the photon detector event scaler is read out. There is one set of buffered counts for every photon event, so the information from the previous step is used. Only the first four words need to be read out because the other channels are not connected. DMA access can speed up this copy operation.
4. If desired, the buffered V792 and V775 events are read out. Threshold suppression of these modules can be used to speed up this operation.
5. Finally the events in the sampling ADC buffer are read out. Block transfers can speed up this copy operation.

The SIS3320 sampling ADC is armed for sampling as soon as the accumulators are read out and the buffer has been swapped. This is early enough to be ready by the time the integration window starts.

The photon detector events are suppressed until after the scalers, V792 and V775 are read out. This ensures that we do not buffer more events than we can handle in the read-out cycle before the next helicity trigger arrives.

Trigger supervisor crate

The trigger supervisor crate is responsible for the helicity and quartet streams. Two methods for helicity read-out are used: user bit mode (SIS3801) and input register mode (SIS3600). The user bits are sometimes latched at the wrong time (one helicity window off), so the input register bit should be trusted. The input register is latched with the rising edge of the ~MPS signal. An additional scaler (STR7200) is used to count the helicity pattern phase. These scaler channels are cleared by the combination of QRT && ~MPS.

In the trigger supervisor crate there are two scaler modules (SIS3801) that read the V/F signals with the BCM and BPM information.

CsI Crystal

After polishing, the transparency improved:

Detector assembly and test

The CsI crystal was wrapped with aluminized mylar and tedlar. The PMT was then glued.

The test results are [here]